FIGS. 1A through C illustrate steps in a conventional semiconductor fabrication process on a portion of a semiconductor wafer 100. In FIG. 1A, a semiconductor substrate 101 is shown. The substrate 101 has a gate oxide layer 104, which will function as a gate dielectric layer, formed on its upper surface 102. The gate oxide layer 104 may be created in ways well known to those of skill in the art. For example, the gate oxide may be silicon dioxide (SiO2) generated by thermal oxidation of surface 102 of the silicon substrate 101, or may be deposited on the silicon substrate 101 by chemical vapor deposition (CVD). Typical conventional gate oxide thicknesses, for example, for semiconductor devices having gate lengths from about 0.18 to 1 μm, are about 25 to 200 Angstroms.
As shown in FIGS. 1B and 1C, a doped polysilicon (poly) layer 106 is typically deposited over the following gate oxide layer 104, for example by in situ doped CVD or undoped CVD followed by implantation and annealing. FIG. 1B shows the wafer 100 with the poly layer 106 on the gate oxide layer 104. FIG. 1C shows the wafer 100 after the poly layer 106 has been patterned and etched to form a gate electrode 108, according to methods well known in the art. The gate electrode 108 may then be used as a mask in a self-aligned implant process that penetrates through the gate oxide layer 104 to produce doped active source 110 and drain 112 regions in the substrate 101, on either side of the gate electrode 108, thereby forming an MOS transistor.
As semiconductor technology has developed, semiconductor device geometries have been reduced. As a result, the various components that make up a semiconductor have been decreased in size. As device sizes decrease, gate dielectric layers in such devices should correspondingly become thinner and provide correspondingly higher capacitance. However, a problem with thinner gate dielectric layers is that such layers allow more leakage current between the gate electrode 108 and the source 110 and/or between the gate electrode 108 and the drain 112. Ideally, a MOS transistor and other semiconductor devices have no leakage current. Leakage current is undesirable because leakage current results in wasted power that requires additional cooling of the device. Another problem caused by leakage current is that device speed is decreased because the magnitude of the signal must rise substantially above the magnitude of the leakage current before the signal can be detected.
An improvement in the manufacture of thin gate dielectrics in high performance CMOS devices includes forming the thin gate dielectrics of silicon oxynitrides (SiOxNy) having less than 10% nitrogen. Advantages of introducing nitrogen into the thin gate dielectric include preventing boron diffusion into the silicon substrate, preventing hot electron degradation, and improving the breakdown resistance of the gate oxide.
One of the major requirements of thin gate dielectrics in CMOS devices is that their gate leakage current densities be less than 1 Amp/cm2 at room temperature. The mechanism governing the magnitude of the leakage current for ultra-thin silicon oxynitride at room temperature is Fowler-Nordheim tunneling. Experimental results have shown that leakage currents are increased by an order of magnitude for every 2 Angstroms reduction in the thickness of the dielectric. This implies that the continued use of silicon oxynitride gate dielectrics for 70 nm technology node transistors will result in leakage currents above 50 Amp/cm2, which is above the acceptable level, particularly for SRAM applications.
The leakage current can be reduced by using a dielectric material including a metal silicate (e.g., ZrxSi1-xO4, HfxSi1-xO4) instead of silicon oxynitride. The metal silicate has a higher dielectric constant (K value) than the silicon oxynitride dielectric. Thus, by using the metal silicate instead of the silicon oxynitride to form the dielectric layer, it is possible to form the dielectric layer with a greater thickness, thereby decreasing leakage current, while still maintaining the same dielectric properties. The metal silicate can maintain chemical stability on silicon, provide 1010-1011/cm2 of interfacial fixed charge density, and provide a large conduction band offset.
One of the important considerations in using silicates is the choice of the ratio between metals and silicon, since this ratio determines the value of the dielectric constant of the silicate. The K value of Hf02Si0.8O4, for example, is about twice that of SiO2. Hf02Si08O4 is a medium K dielectric. Thus, a silicon oxynitride dielectric having a thickness of 12-13 Angstroms (which is about the appropriate thickness for a 70 nm node device) can be replaced by a Hf0.2Si08O4 dielectric having a thickness of 25 Angstroms. The Hf0.2Si08O4 dielectric can be said to have an equivalent thickness or equivalent oxide thickness (EOT) of 12-13 Angstroms. That is, a Hf02Si08O4 dielectric having a thickness of 25 Angstroms provides the same capacitance as a silicon oxynitride dielectric having a thickness of 12-13 Angstroms.
The approach of forming metal silicate dielectrics instead of silicon oxynitride dielectrics requires the formation of thin layers of such silicates on the thin gate areas. The current techniques available for forming these layers include molecular beam epitaxy, sputtering, and metal organic chemical vapor deposition (MOCVD).
Molecular beam epitaxy is an intrinsically slow and low surface coverage deposition technique whose use is confined to scientific laboratories only, and that has no established role in a semiconductor manufacturing environment. Hence, molecular beam epitaxy is not a suitable technique for manufacturing 50-70 nm node devices. Similarly, sputtering also suffers from poor surface coverage, and is again not a suitable technique for depositing gate dielectrics on large silicon wafers.
Although MOCVD deposition technique has a higher surface coverage and higher deposition rates, it has a variety of disadvantages, including difficulty in scaling down the silicate thickness to 20-25 Angstroms. Moreover, when using MOCVD, it is difficult to control the silicate thickness with a 1-2% precision in the 20-25 Angstrom thickness range, which is needed for manufacturing 70 nm node devices. A further disadvantage is that MOCVD tools are not normally part of the existing tool set in semiconductor fabrication facilities, and therefore require additional capital investment. The present commercially available MOCVD tools and their associated deposition process therefore are not directly applicable to the manufacturing of 70 nm node devices.
Thus, a continuing need exists for a method of fabricating a thin gate dielectric that addresses one or more of the above described problems. More particularly, what is needed in the art is a method of increasing the thickness of thin gate dielectrics in order to reduce leakage current, but at the same time retain the high capacitance and performance made possible by thinner gate dielectrics.